Technical Field
Embodiments described herein relate to data processing devices and more particularly, to sorting memory pages in a multi-level memory hierarchy.
Description of the Related Art
Certain emerging memory technologies (e.g., die-stacked memory) have the potential to significantly attack the memory wall problem. In particular, placing one or more three-dimensional stacks of memory inside the same package as the processing units can provide orders of magnitude more bandwidth at significantly lower power costs. Recent research has focused on utilizing the stacked dynamic random-access memory (DRAM) as a large, high-bandwidth last-level cache and coping with the challenges of managing the large tag storage required and the relatively slower latencies of DRAM compared to on-chip static random-access memory (SRAM). However, these approaches require complex changes to the processor and cannot leverage the stacked memory to increase the system's overall memory capacity.